A semiconductor package having a plurality of external connection terminals and a wiring board having the semiconductor package thereon have been conventionally known. For example, JP 2003-188508 A, which corresponds to US 2003/0114024 A1, discloses a wiring board having a ball grid array (BGA) type semiconductor package thereon. The BGA type semiconductor package has a plurality of external connection terminals arranged in a grid.
In the semiconductor package of JP 2003-188508 A, among the external connection terminals arranged in the grid on one surface of a sealed body, each of the external connection terminals other than the external connection terminals located on an outermost square-lap of the grid is adjacent to another external connection terminal in a predetermined area in any of eight directions from each external connection terminal, the eight directions including horizontal directions along a horizontal row of the grid, vertical directions perpendicular to the horizontal directions, and four diagonal directions between the horizontal directions and the vertical directions.
In the wiring board of JP 2003-188508 A, a substrate is provided with a plurality of pads that are arranged in a grid to correspond to the external connection terminals of the semiconductor package. Among the plurality of pads, each of the pads other than the pads located on an outermost square-lap of the grid is adjacent to another pad in a predetermined area in any of eight directions from each pad, the eight directions including horizontal directions along a horizontal row of the grid, vertical directions perpendicular to the horizontal directions, and four diagonal directions between the horizontal directions and the vertical directions.
Further, wirings are extended from the pads other than the pads located on the outermost square-lap of the grid to an external area outside of a semiconductor package arrangement area while passing through in between other pads. Moreover, wirings extended from center pads located at a center area of the semiconductor package arrangement area among the pads are connected to vias that are located in between other pads.
In the wiring board of JP 2003-188508 A, since the plurality of pads is densely arranged in the grid, a minimum value of a clearance between the adjacent pads is equal to less than a predetermined value. Therefore, in a case where a thickness of a surface copper foil on the surface of the wiring board is equal to or greater than a predetermined value and the width of the wirings is large, it is difficult to extend the wiring between the pads without contacting the pads, and to form the vias between the pads without contacting the pads. If the wiring or the via contacts the pad, or if a clearance is not ensured with a predetermined size or more between the wiring and the pad or between the via and the pad, reliability of input and output signals of the semiconductor package, which are conducted through the wiring, is likely to decrease.